1. Field of the Invention
The present invention relates to a display device, and more particularly, to a built-in gate driver having an improved reliability and a display device having the same.
2. Description of the Related Art
Display devices such as an active matrix type (AM) liquid crystal display device (LCD) and an AM organic light emitting display device (OLED), which display an image by driving pixels arranged in an active matrix, are being actively researched.
The AM LCD adjusts a light transmittance of a liquid crystal layer by supplying a data voltage according to image information to pixels arranged in an active matrix, thereby displaying a desired image. The AM LCD includes a liquid crystal panel on which pixels are arranged in a matrix, and a gate driver and a data driver for driving the liquid crystal panel.
A built-in LCD has been developed in which a gate driver and/or a data driver are/is installed on the liquid crystal panel so as to reduce manufacturing costs.
In the case of the built-in driver, the liquid crystal panel and the gate driver are simultaneously manufactured. The data driver may or may not be installed within the built-in LCD.
The gate driver includes a plurality of stages for sequentially supplying output signals to respective gate lines. The data driver may also include a plurality of stages. FIG. 1 is a block diagram of a related art gate driver. Referring to FIG. 1, the related art gate driver is configured using one shift resister. The shift resister includes a plurality of stages ST1 to STn connected in cascade. The shift register includes as many stages ST1 to STn as there are number of gate lines in the liquid crystal panel. For example, when the number of gate lines is 193, the number of stages is 193. An output port of a current stage is connected to an input port of the next stage so that an output signal of the current stage initiates an operation of the next stage. Also, a gate line is connected to an output port of each stage. Accordingly, an output signal of each stage is supplied to the gate line and an input port of the next stage.
Since no previous stage exists before a first stage ST1, a start pulse signal SP (a forcible signal) is inputted to the first stage ST1 to initiate the first stage ST1. The start pulse signal is a pulse synchronized with a vertical sync signal Vsyn.
Two or more clocks C1 and C2 having a voltage pulse of a high state are sequentially inputted to each stage. Although only two clocks are inputted to each stage in FIG. 1, 3 or 4 clocks may be inputted to each stage.
According to this structure, output signals are sequentially outputted from the respective stages and gate lines corresponding to these output signals are selected.
FIG. 2 is a detailed circuit diagram of a first stage of a shift register shown in FIG. 1. Driving waveforms for the circuit shown in FIG. 2 are illustrated in FIG. 3. Although only the first stage is illustrated in FIG. 2 for convenience of description, the other stages have the same transistor structure as the first stage.
Referring to FIG. 2, the first stage ST1 includes first to seventh transistors T1 to T7. The first transistor T1 has a gate and a drain commonly connected to the start pulse signal SP and a source connected to a drain of the second transistor T2. In the case of the other stages, an output signal of a previous stage may be connected to a gate and drain of a first transistor T1.
The second transistor T2 has a gate connected to a second clock C2, a drain connected to the source of the first transistor T1, and a source connected to a node Q.
The third transistor T3 has a gate connected to a node QB, a drain connected to the node Q, and a source connected to a first supply voltage VSS.
The fourth transistor T4 has a gate connected to the second clock C2, a drain connected to a second supply voltage VDD, and a source connected to the node QB.
The fifth transistor T5 has a gate connected to the start pulse signal SP, a drain connected to the node QB, and a source connected to the first supply voltage VSS.
The sixth transistor T6 has a gate connected to the node Q, a drain connected to the first clock C1, and a source connected to the first gate line GL1.
The seventh transistor T7 has a gate connected to the node QB, a drain connected to the first gate line GL1, and a source connected to the first supply voltage VSS.
An operation of the first stage ST1 will be described with reference to FIGS. 2 and 3. Referring to FIG. 3, the first clock C1 generates a first periodic pulse and the second clock C2 generates a second periodic pulse. A phase of the first periodic pulse is opposite to that of the second periodic pulse. The start pulse SP is generated in synchronization with the second clock C2.
Initially, when the second clock C2 and the start pulse signal SP are at a high state and inputted to the shift register, the second transistor T2 is turned on and the start pulse signal SP is charged on the node Q via the first transistor T1. The first transistor T1 serves as a diode. That is, in the first transistor T1, a current flows in the forward direction (from drain to source) and does not flow in the reverse direction (from source to drain). Accordingly, when the start pulse signal SP is at a high state the signal is applied to both the drain and the gate of the first transistor T1. The first transistor T1 is turned on and the start pulse signal SP passes through the first transistor T1. The start pulse signal SP charged on the node Q is blocked by the first transistor T1 and is prevented from being discharged. The node Q is set (that is, initialized) by the start pulse signal SP. While the start pulse signal SP is charged on the node Q, the fourth transistor T4 is turned on by the second clock C2 and the second supply voltage VDD is charge on the node QB. Meanwhile, the fifth transistor T5 is turned on by the start pulse signal SP and thus the node QB is discharged to the first supply voltage VSS. Accordingly, the node QB is maintained at a low voltage.
When the first clock C1 is at a high state, a voltage of the node Q is increased about twice due to a bootstrapping phenomenon caused by a floating state of the node Q.
When the first clock C1 is at a high state, the second clock C2 is at a low state. Due to the second clock C2 being at a low state, the second transistor T2 is turned off and the third transistor T3 is also turned off by the node QB being at a low voltage, causing the node Q to be in a floating state. When the first clock C1 is applied to the sixth transistor T6, the voltage of the node Q is increased by the first clock C1 due to a capacitor Cgd between the gate and drain of the sixth transistor T6. Accordingly, the sixth transistor T6 is turned on and the first clock C1 is outputted as a first output signal Vg1. At this time, the node QB is maintained at a low voltage.
When the second clock C2 is again inputted, the fourth transistor T4 is turned on and the second supply voltage VDD is charged on the node QB. The third and seventh transistors T3 and T7 are turned on by the second supply voltage at the node QB. While the node Q is discharged through the third transistor T3, the first gate line GL1 is discharged through seventh transistor T7. Accordingly, the node Q is reset to the first supply voltage
This process is repeated per frame. That is, the first output signal Vg1 is outputted from the first stage ST1 once per frame. A similar output signal is outputted from each of the remaining stages ST2 to STn once per frame. The respective output signals of the respective stages for each frame are delayed on a clock basis and thus are sequentially outputted.
The above-constructed gate driver generates an output signal of a high state for a very short period and is maintained at a low state during the remaining period.
In order to maintain the output signal at a low state, the node QB must be maintained at a high state. The node QB is maintained at a high state during most of the period in each frame, during which the third and seventh transistors T3 and T7 connected to the node QB receive a considerable bias stress. This bias stress is accumulated at every frame. When the gate driver is driven for a long time, the accumulated bias stress causes the third and seventh transistors T3 and T7 to be degraded, leading to a change in their characteristics (for example, a threshold voltage). A threshold voltage of 1˜2V may be degraded to 10V or higher.
In addition, a driving characteristic of the second transistor T2 is also degraded as shown in Table 1 below. Table 1 shows a change in a characteristic of each transistor when it is driven for 40 hours at 60° C.
TABLE 1TransistorCharacteristic change (ΔVth)T28.6T310.3T40.02T51.3T60.7T79.5
As shown in Table 1, threshold voltages of the third and seventh transistors T3 and T7 are most greatly changed to 10.3 V and 9.5 V, respectively, and a threshold voltage of the second transistor T2 is considerably changed to 8.6 V.
The characteristic change of the third and seventh transistors T3 and T7 leads to their malfunction, causing a plurality of output signals to be outputted in one frame. In the normal state, one stage generates one output signal in one frame. However, when the third and seventh transistors T3 and T7 malfunction, several output signals may be generated in one frame as shown in FIG. 4.
FIG. 4 is a graph illustrating abnormal signals outputted due to the degradation of the gate driver shown in FIG. 1. Referring to FIG. 4, when the third and seventh transistors T3 and T7 are driven for a long time and are degraded, their threshold voltages may be increased. When the threshold voltage is increased, the fourth transistor T4 is turned on by the second clock C2. Although the second supply voltage VDD is charged on the node QB, the third transistor T3 cannot be turned on by the second voltage VDD of the charge node QB. When the third transistor T3 is not turned on, the node Q is not discharged, causing the sixth transistor T6 to be turned on. Periodic pulses of a high state are outputted as the output signals through the sixth transistor T6. Therefore, although one stage must output only one normal output signal in one frame so as to activate the corresponding gate line, abnormal output signals other than the normal output signal is outputted in one frame and the gate lines are frequently activated, causing unwanted pixels to be displayed. These abnormal output signals causes blurring and fluttering, causing degradation in the reliability of the gate driver.
Since the threshold voltage of the second transistor T2 is increased due to the degradation thereof and thus is not turned off, the start pulse signal SP cannot be charged on the node Q. Accordingly, the gate driver is abnormally driven and thus its reliability is degraded.